A digital circuit is an arrangement for providing predetermined output digital signals in response to input digital signals. Such a digital circuit typically takes the form of either a digital memory circuit or a digital logic circuit. In particular, a digital memory circuit is an arrangement for storing digital data in various memory elements that can be accessed for reading in response to memory address signals. In a random access memory circuit, the stored data in any memory element can be changed in accordance with prescribed new data by electrical means. In a read only memory circuit, the stored data cannot be reversibly changed by electrical means.
On the other hand, a digital logic circuit is an arrangement, typically found in a data processing system, for processing digital input data into digital output data in accordance with prescribed logic computation rules. Such logic circuits generally fall into two classes, sequential and combinational. Sequential logic circuits contain clocked memory elements (or clocked registers) and perform their prescribed logic functions or computations in synchronism with an external clock that supplies control timing to their memory elements. Combinational logic circuits have no memory elements and do not require any clocked timing control, although ordinarily new data enters as input to a combination logic circuit on every new cycle of a clock that controls the operation of sequential logic circuits in the same data processing system. Thus, in any event, during each cycle of the clock, a logic circuit performs prescribed computation operations on the digital data in accordance with prescribed rules. The input and output data for a given cycle of the clock each takes the form of an input and an output group of bits, respectively, commonly called an input word and an output word, respectively. The output data of a given cycle can correspond to the desired result of processing the input data of that cycle (combinational logic) and/or of an earlier cycle or cycles (sequential logic).
As manufactured by conventional techniques, however, a logic circuit can have undesirable logic faults, i.e., departures of some of the actual output data words from the desired output as prescribed by the transformation rules, caused by imperfection(s) in the circuit, such as a stuck-fault (a transistor improperly always on or always off regardless of input signal).
One testing approach, one which requires no special design of the logic circuit itself to facilitate the testing, involves simply delivering a sequence of many predetermined input words (test vectors) and comparing the logic circuit's output response word for each such input word with the corresponding expected fault-free word. Any discrepancy between any bit of any such output response word and the corresponding bit of the corresponding expected word indicates the presence of at least one logical fault in the logic circuit. A major disadvantage of this approach is the added cost of extra hardware needed and the added operating time required to generate and store the required test vectors and to deliver them sequentially to the logic circuit, as well as the added cost in operating time required to compare sequentially every one of the output words with the corresponding one of the expected words. The latter disadvantage is especially acute since the required number of such test vectors typically is of the order of hundreds or thousands in order to assure a reasonably high probability (typically at least 80%) of detecting a fault in the logic circuit, i.e., to assure reasonably good fault detection coverage.
In prior Art, therefore, various approaches have been proposed for specially designing logic circuits themselves in such a manner as to facilitate testing to detect the presence of logic faults therein. In general, these approaches involve designing the circuit to render a relatively large number of internal circuit nodes directly accessible for testing, while adding only a few, if any, additional external access terminals or pins to the circuit, as explained in greater detail, for example, in U.S. Pat. No. 4,320,509, entitled "LSI Circuit Logic Structure Including Data Compression Circuitry," by R. P. Davidson, dated Mar. 16, 1982.
In particular, U.S. Pat. No. 3,783,254, issued to E. B. Eichelberger on Jan. 1, 1974, entitled "Level Sensitive Logic System," teaches a logic circuit that can be placed in a test mode in which all latches associated with selected internal nodes are configured into one or more serial shift registers from which data can be serially shifted out of the latches for readout and comparison with the expected fault-free response. An important disadvantage of this approach is that it does not test the circuit at its full rated operating speed, so that high frequency (a.c.) faults may not be detected. Also, testing in accordance with this approach is undesirably time-consuming, because of the need to examine a relatively long output bit stream on a bit-by-bit basis.
Another illustrative approach to improve testability involves generation of a signature word of one or more bits in length by sampling the parity signals present at one or more given internal nodes at different times during operation and arithmetically adding the parity signals together for each node to form a timecompressed parity bit for each node. Such an approach is described, for example, in the aforementioned U.S. Pat. No. 4,320,509. Any discrepancy between the resulting signature word formed by the string of such compressed parity bits for each node and the expected fault-free signature word supplies the desired error information concerning the data on each of the internal nodes. Important disadvantages of this approach are that it requires an undesirably large number of additional access terminals and that testing of the added test circuitry itself for its own errors is not easily accomplished.
Moreoever, similar and further problems arise in the testing of digital memory circuits. In such memory circuits, generally, pattern dependent faults may occur; that is, an error in a given storage element does or does not occur depending upon the instantaneous pattern of data then stored in other elements of the memory. Hence, testing memory circuits for faults generally presents a problem that is of even greater complexity than testing for faults in logic circuits of similar size.
It would therefore be desirable to have a means for reasonably good fault detection coverage of a digital circuit that mitigates the problems of the prior art.